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Date: Sun, 19 Jul 2015 07:27:15 -0700
From: Bill Cox <>
To: "" <>
Subject: Re: [PHC] Bandwidth hardened algorithms?

On Thu, Jul 16, 2015 at 4:38 PM, Dmitry Khovratovich <
> wrote:

> I see your point. But don't you overestimate the ASIC cost? As there is
> little logic beyond the memory itself, the parallel chip can be as cheap as
> the 32 GB unit, i.e. 180$
> Dmitry

I am underestimating the ASIC cost in the extreme case where a buyer buys
many millions of dollars worth.  A lot of the pricing depends on volume.
They'd have to buy many millions of dollars worth to get the best pricing,
but I suppose BitCoin mining might support that.

High bandwidth ASICs and the systems they go into are tricky.  For example,
Achronix only sells their FPGAs to a few big customers.  You can't buy
one.  When you have 10 GiB/s I/O pins, you can't just let anybody try to
build a board using them.  Instead you have to get involved with the
customer in their board design.  I heard that the Rocket I/O project at
Xilinx slowed down their FPGA development to a point that it did major
damage to the company, and these I/Os are 3X slower than the Achronix I/Os
per pin.

I think DRAM pricing shows a good example of how cheap high bandwidth
devices can be.  The highest bandwidth devices are quite a bit more
expensive.  It is not clear how much the actual RAM costs vs the I/Os in
these parts.


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