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Date: Fri, 28 Aug 2015 18:29:36 +0000
From: Marsh Ray <>
To: "" <>
Subject: RE: [PHC] Flaw in Argon2 TMTO ASIC analysis

Perhaps we should keep an eye on the 3D chip stacking technology. It’s been discussed for many years, but is just recently starting to come online.

E.g. “the CMOSAIC project considers a 3D stack-architecture of multiple cores with a interconnect density from 100 to 10,000 connections per millimeter square”

Seems like that could represent a pretty big jump in memory bandwidth.

-          Marsh

From: Bill Cox []
Sent: Friday, August 28, 2015 7:32 AM
Subject: Re: [PHC] Flaw in Argon2 TMTO ASIC analysis

It's proportional to the number of I/Os, which on most ASICs is proportional to sqrt(area).

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