linux-kernel - Re: [PATCH] x86: Support always running TSC on Intel CPUs

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Date:	Mon, 17 Nov 2008 16:49:19 -0800
From:	Venki Pallipadi <venkatesh.pallipadi@...el.com>
To:	"H. Peter Anvin" <hpa@...or.com>
Cc:	"Pallipadi, Venkatesh" <venkatesh.pallipadi@...el.com>,
	Ingo Molnar <mingo@...e.hu>,
	Thomas Gleixner <tglx@...utronix.de>,
	linux-kernel <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] x86: Support always running TSC on Intel CPUs

On Mon, Nov 17, 2008 at 04:18:16PM -0800, H. Peter Anvin wrote:
> Pallipadi, Venkatesh wrote:
> > 
> > All C-states higher than C1. 
> > 
> 
> Including C2?  If so, the TSC is unusable since C2 can be invoked 
> asynchronously by the chipset.
> 

No. Not on Intel CPUs atleast. On Intel CPUs, we enter C-states only on
hlt or mwait. C1 is always C1 or C1E, where TSC always runs.
C2, C3, ... implementation vary depending on processor and TSC may or may
not run. This 0x80000007 feature bit basically says TSC is going to run
during any C-state.

Thanks,
Venki
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