linux-kernel - Re: [PATCH] x86: Support always running TSC on Intel CPUs

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:	Mon, 17 Nov 2008 16:52:21 -0800
From:	"H. Peter Anvin" <hpa@...or.com>
To:	Venki Pallipadi <venkatesh.pallipadi@...el.com>
CC:	Ingo Molnar <mingo@...e.hu>, Thomas Gleixner <tglx@...utronix.de>,
	linux-kernel <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] x86: Support always running TSC on Intel CPUs

Venki Pallipadi wrote:
> On Mon, Nov 17, 2008 at 04:18:16PM -0800, H. Peter Anvin wrote:
>> Pallipadi, Venkatesh wrote:
>>> All C-states higher than C1. 
>>>
>> Including C2?  If so, the TSC is unusable since C2 can be invoked 
>> asynchronously by the chipset.
>>
> 
> No. Not on Intel CPUs atleast. On Intel CPUs, we enter C-states only on
> hlt or mwait.  C1 is always C1 or C1E, where TSC always runs.
> C2, C3, ... implementation vary depending on processor and TSC may or may
> not run. This 0x80000007 feature bit basically says TSC is going to run
> during any C-state.
> 

I was under the impression that C2 was invoked by the chipset on a 
thermal condition, at least on older (P3-era) processors.  Is that no 
longer true?  If what you say is above (HLT and MWAIT only), then *was* 
it ever true?

	-hpa

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/