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Date: Tue, 24 Nov 2015 20:15:42 +0800
From: kbuild test robot <lkp@...el.com>
To: Joao Pinto <Joao.Pinto@...opsys.com>
Cc: kbuild-all@...org, linux-pci@...r.kernel.org,
linux-kernel@...r.kernel.org, bhelgaas@...gle.com,
CARLOS.PALMINHA@...opsys.com, Vineet.Gupta1@...opsys.com,
Alexey.Brodkin@...opsys.com, Joao Pinto <Joao.Pinto@...opsys.com>
Subject: Re: [PATCH 1/2] add new platform driver for PCI RC
Hi Joao,
[auto build test ERROR on arc/for-next]
[also build test ERROR on v4.4-rc2 next-20151124]
url: https://github.com/0day-ci/linux/commits/Joao-Pinto/add-new-platform-driver-for-PCI-RC/20151124-194755
base: https://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc for-next
config: i386-allmodconfig (attached as .config)
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
All errors (new ones prefixed by >>):
drivers/pci/host/pcie-designware.c: In function 'dw_pcie_host_init':
drivers/pci/host/pcie-designware.c:555:7: error: implicit declaration of function 'pci_has_flag' [-Werror=implicit-function-declaration]
if (!pci_has_flag(PCI_PROBE_ONLY)) {
^
drivers/pci/host/pcie-designware.c:555:20: error: 'PCI_PROBE_ONLY' undeclared (first use in this function)
if (!pci_has_flag(PCI_PROBE_ONLY)) {
^
drivers/pci/host/pcie-designware.c:555:20: note: each undeclared identifier is reported only once for each function it appears in
drivers/pci/host/pcie-designware.c: In function 'dw_pcie_link_retrain':
>> drivers/pci/host/pcie-designware.c:713:23: error: 'LINK_CONTROL_LINK_STATUS_REG' undeclared (first use in this function)
dw_pcie_readl_rc(pp, LINK_CONTROL_LINK_STATUS_REG, &val);
^
>> drivers/pci/host/pcie-designware.c:714:14: error: 'PCIE_RETRAIN_LINK_MASK' undeclared (first use in this function)
val = val | PCIE_RETRAIN_LINK_MASK;
^
cc1: some warnings being treated as errors
vim +/LINK_CONTROL_LINK_STATUS_REG +713 drivers/pci/host/pcie-designware.c
549
550 #ifdef CONFIG_ARM
551 /* support old dtbs that incorrectly describe IRQs */
552 pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
553 #endif
554
> 555 if (!pci_has_flag(PCI_PROBE_ONLY)) {
556 pci_bus_size_bridges(bus);
557 pci_bus_assign_resources(bus);
558
559 list_for_each_entry(child, &bus->children, node)
560 pcie_bus_configure_settings(child);
561 }
562
563 pci_bus_add_devices(bus);
564 return 0;
565 }
566
567 static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
568 u32 devfn, int where, int size, u32 *val)
569 {
570 int ret, type;
571 u32 busdev, cfg_size;
572 u64 cpu_addr;
573 void __iomem *va_cfg_base;
574
575 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
576 PCIE_ATU_FUNC(PCI_FUNC(devfn));
577
578 if (bus->parent->number == pp->root_bus_nr) {
579 type = PCIE_ATU_TYPE_CFG0;
580 cpu_addr = pp->cfg0_base;
581 cfg_size = pp->cfg0_size;
582 va_cfg_base = pp->va_cfg0_base;
583 } else {
584 type = PCIE_ATU_TYPE_CFG1;
585 cpu_addr = pp->cfg1_base;
586 cfg_size = pp->cfg1_size;
587 va_cfg_base = pp->va_cfg1_base;
588 }
589
590 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
591 type, cpu_addr,
592 busdev, cfg_size);
593 ret = dw_pcie_cfg_read(va_cfg_base + where, size, val);
594 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
595 PCIE_ATU_TYPE_IO, pp->io_base,
596 pp->io_bus_addr, pp->io_size);
597
598 return ret;
599 }
600
601 static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
602 u32 devfn, int where, int size, u32 val)
603 {
604 int ret, type;
605 u32 busdev, cfg_size;
606 u64 cpu_addr;
607 void __iomem *va_cfg_base;
608
609 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
610 PCIE_ATU_FUNC(PCI_FUNC(devfn));
611
612 if (bus->parent->number == pp->root_bus_nr) {
613 type = PCIE_ATU_TYPE_CFG0;
614 cpu_addr = pp->cfg0_base;
615 cfg_size = pp->cfg0_size;
616 va_cfg_base = pp->va_cfg0_base;
617 } else {
618 type = PCIE_ATU_TYPE_CFG1;
619 cpu_addr = pp->cfg1_base;
620 cfg_size = pp->cfg1_size;
621 va_cfg_base = pp->va_cfg1_base;
622 }
623
624 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
625 type, cpu_addr,
626 busdev, cfg_size);
627 ret = dw_pcie_cfg_write(va_cfg_base + where, size, val);
628 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
629 PCIE_ATU_TYPE_IO, pp->io_base,
630 pp->io_bus_addr, pp->io_size);
631
632 return ret;
633 }
634
635 static int dw_pcie_valid_config(struct pcie_port *pp,
636 struct pci_bus *bus, int dev)
637 {
638 /* If there is no link, then there is no device */
639 if (bus->number != pp->root_bus_nr) {
640 if (!dw_pcie_link_up(pp))
641 return 0;
642 }
643
644 /* access only one slot on each root port */
645 if (bus->number == pp->root_bus_nr && dev > 0)
646 return 0;
647
648 /*
649 * do not read more than one device on the bus directly attached
650 * to RC's (Virtual Bridge's) DS side.
651 */
652 if (bus->primary == pp->root_bus_nr && dev > 0)
653 return 0;
654
655 return 1;
656 }
657
658 static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
659 int size, u32 *val)
660 {
661 struct pcie_port *pp = bus->sysdata;
662 int ret;
663
664 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
665 *val = 0xffffffff;
666 return PCIBIOS_DEVICE_NOT_FOUND;
667 }
668
669 if (bus->number != pp->root_bus_nr)
670 if (pp->ops->rd_other_conf)
671 ret = pp->ops->rd_other_conf(pp, bus, devfn,
672 where, size, val);
673 else
674 ret = dw_pcie_rd_other_conf(pp, bus, devfn,
675 where, size, val);
676 else
677 ret = dw_pcie_rd_own_conf(pp, where, size, val);
678
679 return ret;
680 }
681
682 static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
683 int where, int size, u32 val)
684 {
685 struct pcie_port *pp = bus->sysdata;
686 int ret;
687
688 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
689 return PCIBIOS_DEVICE_NOT_FOUND;
690
691 if (bus->number != pp->root_bus_nr)
692 if (pp->ops->wr_other_conf)
693 ret = pp->ops->wr_other_conf(pp, bus, devfn,
694 where, size, val);
695 else
696 ret = dw_pcie_wr_other_conf(pp, bus, devfn,
697 where, size, val);
698 else
699 ret = dw_pcie_wr_own_conf(pp, where, size, val);
700
701 return ret;
702 }
703
704 static struct pci_ops dw_pcie_ops = {
705 .read = dw_pcie_rd_conf,
706 .write = dw_pcie_wr_conf,
707 };
708
709 void dw_pcie_link_retrain(struct pcie_port *pp)
710 {
711 u32 val = 0;
712
> 713 dw_pcie_readl_rc(pp, LINK_CONTROL_LINK_STATUS_REG, &val);
> 714 val = val | PCIE_RETRAIN_LINK_MASK;
715 dw_pcie_writel_rc(pp, val, LINK_CONTROL_LINK_STATUS_REG);
716 }
717
---
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