lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Mon, 26 Feb 2018 11:01:17 +0800
From:   Baolin Wang <baolin.wang@...aro.org>
To:     Andy Shevchenko <andy.shevchenko@...il.com>
Cc:     Linus Walleij <linus.walleij@...aro.org>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        devicetree <devicetree@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
        Mark Brown <broonie@...nel.org>
Subject: Re: [PATCH v2 3/3] gpio: Add Spreadtrum PMIC EIC driver support

Hi Andy,

On 25 February 2018 at 20:19, Andy Shevchenko <andy.shevchenko@...il.com> wrote:
> On Sat, Feb 24, 2018 at 12:44 PM, Baolin Wang <baolin.wang@...aro.org> wrote:
>> The Spreadtrum PMIC EIC controller contains only one bank of debounce EIC,
>> and this bank contains 16 EICs. Each EIC can only be used as input mode,
>> as well as supporting the debounce and the capability to trigger interrupts
>> when detecting input signals.
>
>> +/*
>> + * These registers are modified under the irq bus lock and cached to avoid
>> + * unnecessary writes in bus_sync_unlock.
>> + */
>> +enum { REG_IEV, REG_IE, REG_TRIG, CACHE_NR_REGS };
>
> One item per line.

Sure.

>
>> +static int sprd_pmic_eic_direction_input(struct gpio_chip *chip,
>> +                                        unsigned int offset)
>> +{
>> +       /* EICs are always input, nothing need to do here. */
>> +       return 0;
>> +}
>> +
>> +static void sprd_pmic_eic_set(struct gpio_chip *chip, unsigned int offset,
>> +                             int value)
>> +{
>> +       /* EICs are always input, nothing need to do here. */
>> +}
>
> Remove both.
>
> Look at what GPIO core does.

I've checked the GPIO core, we need the
sprd_pmic_eic_direction_input() returns 0, since user can set GPIOD_IN
flag when requesting one GPIO, otherwise it will return errors.
We also need one dummy sprd_pmic_eic_set() when setting debounce for
one GPIO, otherwise it will return errors.

>
>> +       value |= debounce / 1000;
>
> Possible overflow.

OK. I should & SPRD_PMIC_EIC_DBC_MASK.

>
>> +       for (n = 0; n < chip->ngpio; n++) {
>> +               if (!(BIT(n) & val))
>
> for_each_set_bit().
>
> At some point you may need just to go across lib/ in the kernel and
> see what we have there.

I've considered the for_each_set_bit(), it need one 'unsigned long'
type parameter, but we get the value from regmap is 'u32' type. So we
need one extra conversion from 'u32' to 'unsigned long' like:

unsigned long reg = val;

for_each_set_bit(n, &reg, chip->ngpio) {
        .......
}

If you like this conversion, then I can change to use
for_each_set_bit(). Thanks.

-- 
Baolin.wang
Best Regards

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ