netdev - Re: [PATCH] phy/micrel: KSZ8031RNL RMII clock reconfiguration bug

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Date:	Tue, 14 Oct 2014 12:41:17 -0400 (EDT)
From:	David Miller <davem@...emloft.net>
To:	bth@...strup.dk
Cc:	netdev@...r.kernel.org, f.fainelli@...il.com,
	s.hauer@...gutronix.de, bruno.thomsen@...il.com
Subject: Re: [PATCH] phy/micrel: KSZ8031RNL RMII clock reconfiguration bug

From: Bruno Thomsen <bth@...strup.dk>
Date: Thu, 9 Oct 2014 16:48:14 +0200

> Bug: Unable to send and receive Ethernet packets with Micrel PHY.
> 
> Affected devices:
> KSZ8031RNL (commercial temp)
> KSZ8031RNLI (industrial temp)
> 
> Description:
> PHY device is correctly detected during probe.
> PHY power-up default is 25MHz crystal clock input
> and output 50MHz RMII clock to MAC.
> Reconfiguration of PHY to input 50MHz RMII clock from MAC
> causes PHY to become unresponsive if clock source is changed
> after Operation Mode Strap Override (OMSO) register setup.
> 
> Cause:
> Long lead times on parts where clock setup match circuit design
> forces the usage of similar parts with wrong default setup.
> 
> Solution:
> Swapped KSZ8031 register setup and added phy_write return code validation.
> 
> Tested with Freescale i.MX28 Fast Ethernet Controler (fec).
> 
> Signed-off-by: Bruno Thomsen <bth@...strup.dk>

Applied, thank you.
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