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Date: Sat, 1 Jul 2023 16:00:56 +0800
From: Jie Luo <quic_luoj@...cinc.com>
To: Andrew Lunn <andrew@...n.ch>
CC: <hkallweit1@...il.com>, <davem@...emloft.net>, <edumazet@...gle.com>,
        <kuba@...nel.org>, <pabeni@...hat.com>, <linux@...linux.org.uk>,
        <netdev@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 1/3] net: phy: at803x: support qca8081 1G chip type



On 6/30/2023 9:16 PM, Andrew Lunn wrote:
> On Fri, Jun 30, 2023 at 02:39:06PM +0800, Jie Luo wrote:
>>
>>
>> On 6/29/2023 9:14 PM, Andrew Lunn wrote:
>>> On Thu, Jun 29, 2023 at 11:48:44AM +0800, Luo Jie wrote:
>>>> The qca8081 1G chip version does not support 2.5 capability, which
>>>> is distinguished from qca8081 2.5G chip according to the bit0 of
>>>> register mmd7.0x901d.
>>>>
>>>> The fast retrain and master slave seed configs are only needed when
>>>> the 2.5G capability is supported.
>>>
>>> Does genphy_c45_pma_read_abilities() work on these devices?
>>>
>>>        Andrew
>>
>> Hi Andrew,
>> yes, genphy_c45_pma_read_abilities works on both normal qca8081 2.5G chip
>> and qca8081 1G version chip, even the PHY ID is same, the only difference
>> between qca8081 1G and 2.5G chip is the 2.5G capability removed on 1G
>> version chip.
> 
> Great, then please use it to simply the driver.
> 
>         Andrew
Hi Andrew,
Per double check qca8081 PHY registers, the PHY ID only exists in the 
MII register, which is not in the MMD device register.

There are MMD device 1, 3, 7 in qca8081 PHY, the PMA abilities 
10/100/1000/2500 are compliant with genphy_c45_pma_read_abilities, but 
the MDIO_AN_STAT1_ABLE does not exist in MMD7.1 register.

so the genphy_c45_pma_read_abilities can't be fully supported by qca8081 
phy, sorry for this misunderstanding.

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