full-disclosure - Cisco IOS Shellcode Presentation

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Message-ID: <200507292110.j6TLACDF000303@turing-police.cc.vt.edu>
Date: Fri Jul 29 22:10:25 2005
From: Valdis.Kletnieks at vt.edu (Valdis.Kletnieks@...edu)
Subject: Cisco IOS Shellcode Presentation 

On Fri, 29 Jul 2005 15:33:19 CDT, Randall Perry said:

> Even for producing less than 500 units there are vendors ready to jump at the
> chance to replace FPGA setups (because we are talking about complex 2k+ gate count).

More like 2M+ gate count.  Remember, you have to do BGP4 in silicon. ;)

> Just give Oxford Semiconductor or AMI a call.

I don't think Oxford Semiconductor would be able to deal - looks like they're
mostly in the FireWire/USB arena.  AMI has a 2M gate part, but it has a top
clock speed of 100Mhz (http://www.amis.com/asics/structured_asics/XPressArray.html),
which would be borderline in the high-end routers....

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