linux-kernel - Re: [MODSLAB 3/7] A Kmalloc subsystem

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Message-ID: <44E75E56.60905@colorfullife.com>
Date:	Sat, 19 Aug 2006 20:54:14 +0200
From:	Manfred Spraul <manfred@...orfullife.com>
To:	Christoph Lameter <clameter@....com>
CC:	Andi Kleen <ak@....de>, mpm@...enic.com,
	Marcelo Tosatti <marcelo@...ck.org>,
	linux-kernel@...r.kernel.org,
	Nick Piggin <nickpiggin@...oo.com.au>, Andi Kleen <ak@...e.de>,
	Dave Chinner <dgc@....com>
Subject: Re: [MODSLAB 3/7] A Kmalloc subsystem

Christoph Lameter wrote:

>On Sat, 19 Aug 2006, Manfred Spraul wrote:
>  
>
>>What about:
>>
>>if (unlikely(addr & (~(PAGE_SIZE-1))))
>>   slabp=virt_to_page(addr)->pagefield;
>>else
>>   slabp=addr & (~(PAGE_SIZE-1));
>>    
>>
>
>Well this would not be working with the simple slab design that puts the 
>first element at the page border to simplify alignment.
>
>And as we have just seen virt to page is mostly an address 
>calculation in many configurations. I doubt that there would be a great 
>advantage. Todays processors biggest cause for latencies are 
>cacheline misses..
>
It involves table walking on discontigmem archs. "slabp=addr & 
(~(PAGE_SIZE-1));" means no pointer chasing, and the access touches the 
same page, i.e. definitively no TLB miss.

> Some arithmetic with addresses does not seem to 
>be that important. Misaligning data in order to not put objects on such
>boundaries could be an issue.
>
> > Modify the kmalloc caches slightly and use non-power-of-2 cache sizes. Move
>  
>
>>the kmalloc(PAGE_SIZE) users to gfp.
>>    
>>
>
>Power of 2 cache sizes make the object align neatly to cacheline 
>boundaries and make them fit tightly into a page.
>  
>
IMHO not really an issue. 2kb-cache_line_size() also aligns perfectly.

--
    Manfred
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