linux-kernel - Re: [MODSLAB 3/7] A Kmalloc subsystem

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Message-ID: <Pine.LNX.4.64.0608191209370.4890@schroedinger.engr.sgi.com>
Date:	Sat, 19 Aug 2006 12:17:13 -0700 (PDT)
From:	Christoph Lameter <clameter@....com>
To:	Manfred Spraul <manfred@...orfullife.com>
cc:	Andi Kleen <ak@....de>, mpm@...enic.com,
	Marcelo Tosatti <marcelo@...ck.org>,
	linux-kernel@...r.kernel.org,
	Nick Piggin <nickpiggin@...oo.com.au>, Andi Kleen <ak@...e.de>,
	Dave Chinner <dgc@....com>
Subject: Re: [MODSLAB 3/7] A Kmalloc subsystem

On Sat, 19 Aug 2006, Manfred Spraul wrote:

> > And as we have just seen virt to page is mostly an address calculation in
> > many configurations. I doubt that there would be a great advantage. Todays
> > processors biggest cause for latencies are cacheline misses..
> > 
> It involves table walking on discontigmem archs. "slabp=addr &
> (~(PAGE_SIZE-1));" means no pointer chasing, and the access touches the same
> page, i.e. definitively no TLB miss.

There is no table walking for discontigmem on ia64. Ia64 only creates page 
table if it needs to satify the Linux kernels demands for such a thing. 
And this is a kernel mapping. No page table involved.

The current sparsemem approach also does not need table walking. It needs
to do lookups in a table.

UP and SMP currently work cleanly.

> > Power of 2 cache sizes make the object align neatly to cacheline boundaries
> > and make them fit tightly into a page.
> >  
> IMHO not really an issue. 2kb-cache_line_size() also aligns perfectly.

That would work and also be in line with the existing overhead of the 
slabs.




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