linux-kernel - Re: question regarding cacheline size

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:	Thu, 07 Sep 2006 14:53:57 +0200
From:	Tejun Heo <htejun@...il.com>
To:	Matthew Wilcox <matthew@....cx>
CC:	Arjan van de Ven <arjan@...radead.org>,
	linux-pci@...ey.karlin.mff.cuni.cz, Greg KH <greg@...ah.com>,
	lkml <linux-kernel@...r.kernel.org>
Subject: Re: question regarding cacheline size

Matthew Wilcox wrote:
> On Thu, Sep 07, 2006 at 02:33:25PM +0200, Arjan van de Ven wrote:
>>> So I think we should redo the PCI subsystem to set cacheline size during
>>> the buswalk rather than waiting for drivers to ask for it to be set.
>> ... while allowing for quirks for devices that go puke when this
>> register gets written ;)
>>
>> (afaik there are a few)
> 
> So you want:
> 
> 	unsigned int no_cls:1;	/* Device pukes on write to Cacheline Size */
> 
> in struct pci_dev?

The spec says that devices can put additional restriction on supported 
cacheline size (IIRC, the example was something like power of two >= or 
<= certain size) and should ignore (treat as zero) if unsupported value 
is written.  So, there might be need for more low level driver 
involvement which knows device restrictions, but I don't know whether 
such devices exist.

-- 
tejun
-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/