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Message-ID: <32145.1158051703@warthog.cambridge.redhat.com>
Date: Tue, 12 Sep 2006 10:01:43 +0100
From: David Howells <dhowells@...hat.com>
To: paulmck@...ibm.com
Cc: Alan Stern <stern@...land.harvard.edu>,
Oliver Neukum <oliver@...kum.org>,
David Howells <dhowells@...hat.com>,
Kernel development list <linux-kernel@...r.kernel.org>
Subject: Re: Uses for memory barriers
Paul E. McKenney <paulmck@...ibm.com> wrote:
> 2. All stores to a given single memory location will be perceived
> as having occurred in the same order by all CPUs.
Does that take into account a CPU combining or discarding coincident memory
operations?
For instance, a CPU asked to issue two writes to the same location may discard
the first if it hasn't done it yet.
David
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