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Date: Fri, 06 Oct 2006 15:59:57 -0400 From: Jeff Garzik <jeff@...zik.org> To: Matthew Wilcox <matthew@....cx> CC: Val Henson <val_henson@...ux.intel.com>, Greg Kroah-Hartman <gregkh@...e.de>, netdev@...r.kernel.org, linux-pci@...ey.karlin.mff.cuni.cz, linux-kernel@...r.kernel.org, David Miller <davem@...emloft.net> Subject: Re: [PATCH 2/2] [TULIP] Check the return value from pci_set_mwi() Matthew Wilcox wrote: > On Fri, Oct 06, 2006 at 03:15:15PM -0400, Jeff Garzik wrote: >> Matthew Wilcox wrote: >>> Also, pci_set_mwi() will fail if the cache line >>> size is 0, so we don't need to check that ourselves any more. >> NAK, not true on all arches. sparc64 at least presumes that the >> firmware DTRT with cacheline size, which hurts us now given this tulip patch > > How does it hurt us? > > int pcibios_prep_mwi(struct pci_dev *dev) > { > /* We set correct PCI_CACHE_LINE_SIZE register values for every > * device probed on this platform. So there is nothing to check > * and this always succeeds. > */ > return 0; > } > > If Dave's wrong about that, it hurts him, not us ;-) > > It's still not necessary for the Tulip driver to check. The unmodified tulip driver checks both MWI and cacheline-size because one of the clones (PNIC or PNIC2) will let you set the MWI bit, but hardwires cacheline size to zero. If the arches do not behave consistently, we need to keep the check in the tulip driver, to avoid incorrectly programming the csr0 MWI bit. Jeff - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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