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Message-ID: <adaejswbid4.fsf@cisco.com>
Date:	Wed, 25 Oct 2006 07:05:59 -0700
From:	Roland Dreier <rdreier@...co.com>
To:	Jack Steiner <steiner@....com>
Cc:	Matthew Wilcox <matthew@....cx>, Jeff Garzik <jeff@...zik.org>,
	linux-pci@...ey.karlin.mff.cuni.cz, linux-ia64@...r.kernel.org,
	linux-kernel@...r.kernel.org, openib-general@...nib.org,
	John Partridge <johnip@....com>
Subject: Re: Ordering between PCI config space writes and MMIO reads?

 > I'll check if there is any additional reordering that can occur AFTER the
 > PIO_WRITE_COUNT goes to zero.  If so, it would be at bus level - not in
 > shub or routers.

Unfortunately, at least in theory, the reordering can occur.  For
example a bridge on some card plugged into an SN slot is allowed to
reorder things too.

 - R.
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