linux-kernel - Re: AMD X2 unsynced TSC fix?

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Message-Id: <200610280246.42384.ak@suse.de>
Date:	Sat, 28 Oct 2006 02:46:41 -0700
From:	Andi Kleen <ak@...e.de>
To:	thockin@...kin.org
Cc:	Andrew Morton <akpm@...l.org>,
	Sergio Monteiro Basto <sergio@...giomb.no-ip.org>,
	Lee Revell <rlrevell@...-job.com>,
	Chris Friesen <cfriesen@...tel.com>,
	linux-kernel <linux-kernel@...r.kernel.org>,
	john stultz <johnstul@...ibm.com>
Subject: Re: AMD X2 unsynced TSC fix?


> Nothing at all, or just the the low few bits are writeable?  I had heard,
> but never seen that some Intel CPUs only allowed 16 bits of writable bits
> in the TSC MSR.  I also heard of, but never saw, CPUs that cleared the TSC
> to 0 on a write!

Normally on Intel you can only write the first 32bits

-Andi

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