linux-kernel - Re: Ordering between PCI config space writes and MMIO reads?

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Message-ID: <adad588tijq.fsf@cisco.com>
Date:	Tue, 31 Oct 2006 11:02:49 -0800
From:	Roland Dreier <rdreier@...co.com>
To:	linux-kernel@...r.kernel.org
Cc:	David Miller <davem@...emloft.net>, matthew@....cx,
	jeff@...zik.org, linux-pci@...ey.karlin.mff.cuni.cz,
	linux-ia64@...r.kernel.org, openib-general@...nib.org,
	johnip@....com
Subject: Re: Ordering between PCI config space writes and MMIO reads?

The discussion fizzled out without really reaching a definitive
answer, so I'm going to apply the original patch (below), since I
pretty much convinced myself that only the driver doing the config
access has enough information to fix this reliably.

 - R.

Author: John Partridge <johnip@....com>
Date:   Tue Oct 31 11:00:04 2006 -0800

    IB/mthca: Make sure all PCI config writes reach device before doing MMIO
    
    During initialization, mthca writes some PCI config space registers
    and then does an MMIO read from one of the BARs it just enabled.  This
    MMIO read sometimes failed and caused a crash on SGI Altix machines,
    because the PCI-X host bridge (legitimately, according to the PCI
    spec) allowed the MMIO read to start before the config write completed.
    
    To fix this, add a config read after all config writes to make sure
    they are all done before starting the MMIO read.
    
    Signed-off-by: John Partridge <johnip@....com>
    Signed-off-by: Roland Dreier <rolandd@...co.com>

diff --git a/drivers/infiniband/hw/mthca/mthca_reset.c b/drivers/infiniband/hw/mthca/mthca_reset.c
index 91934f2..578dc7c 100644
--- a/drivers/infiniband/hw/mthca/mthca_reset.c
+++ b/drivers/infiniband/hw/mthca/mthca_reset.c
@@ -281,6 +281,20 @@ good:
 		goto out;
 	}
 
+	/*
+	 * Perform a "flush" of the PCI config writes here by reading
+	 * the PCI_COMMAND register.  This is needed to make sure that
+	 * we don't try to touch other PCI BARs before the config
+	 * writes are done -- otherwise an MMIO cycle could start
+	 * before the config writes are done and reach the HCA before
+	 * the BAR is actually enabled.
+	 */
+	if (pci_read_config_dword(mdev->pdev, PCI_COMMAND, hca_header)) {
+		err = -ENODEV;
+		mthca_err(mdev, "Couldn't access HCA memory after restoring, "
+			  "aborting.\n");
+	}
+
 out:
 	if (bridge)
 		pci_dev_put(bridge);
-
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