linux-kernel - Re: SATA exceptions with 2.6.20-rc5

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Message-id: <45B3E87F.4080400@shaw.ca>
Date:	Sun, 21 Jan 2007 16:26:07 -0600
From:	Robert Hancock <hancockr@...w.ca>
To:	Björn Steinbrink <B.Steinbrink@....de>,
	Robert Hancock <hancockr@...w.ca>,
	Jeff Garzik <jeff@...zik.org>, Chr <chunkeey@....de>,
	Alistair John Strachan <s0348365@....ed.ac.uk>,
	linux-kernel@...r.kernel.org, htejun@...il.com,
	jens.axboe@...cle.com, lwalton@...l.com
Subject: Re: SATA exceptions with 2.6.20-rc5

Björn Steinbrink wrote:
> On 2007.01.21 23:08:11 +0100, Björn Steinbrink wrote:
>> On 2007.01.21 13:58:01 -0600, Robert Hancock wrote:
>>> Björn Steinbrink wrote:
>>>> All kernels were bad using that approach. So back to square 1. :/
>>>>
>>>> Björn
>>>>
>>> OK guys, here's a new patch to try against 2.6.20-rc5:
>>>
>>> Right now when switching between ADMA mode and legacy mode (i.e. when 
>>> going from doing normal DMA reads/writes to doing a FLUSH CACHE) we just 
>>> set the ADMA GO register bit appropriately and continue with no delay. 
>>> It looks like in some cases the controller doesn't respond to this 
>>> immediately, it takes some nanoseconds for the controller's status 
>>> registers to reflect the change that was made. It's possible that if we 
>>> were trying to issue commands during this time, the controller might not 
>>> react properly. This patch adds some code to wait for the status 
>>> register to change to the state we asked for before continuing.
>> I went for the "I feel lucky" route and did just add mmio reads after the
>> mmio writes, posting them. Rationale being that if it is a write posting
>> issue, the debug patch would/could actually hide it AFAICT.
>> It's the "I feel lucky" route, because my whole "knowledge" about mmio
>> and write posting originates from the few things I read up on when you
>> discovered the comment about write posting in the generic ata code.
> 
> Uhm, yeah, exception occured about the time that I hit "send".
> 
> Björn

Yeah, I don't think just adding reads to flush posted writes is enough 
here - it seems to need more delay than that, and it also wasn't always 
in the idle state even before we would write the register..

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