linux-kernel - Re: [PATCH] trim memory not covered by WB MTRRs

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Message-ID: <20070626153911.GC5244@one.firstfloor.org>
Date:	Tue, 26 Jun 2007 17:39:11 +0200
From:	Andi Kleen <andi@...stfloor.org>
To:	"Eric W. Biederman" <ebiederm@...ssion.com>
Cc:	Jesse Barnes <jesse.barnes@...el.com>,
	Andi Kleen <andi@...stfloor.org>, linux-kernel@...r.kernel.org,
	akpm@...ux-foundation.org, Justin Piszcz <jpiszcz@...idpixels.com>,
	Yinghai Lu <yhlu.kernel@...il.com>
Subject: Re: [PATCH] trim memory not covered by WB MTRRs

> For the K7 and K8 cores AMD systems are exactly like Intel systems
> with respect to MTRRs (although AMD systems also have additional registers)
> For the K9 core (i.e. AMD socket F or the K8 with DDR2 support) there

It's called K8RevE, not K9

> is an additional mechanism that makes everything above 4G write-back
> cacheable without using any MTRRs.

... but not BIOS use this mechanism (often there are BIOS switches
for several MTRR models or it is just the wrong one hardcoded), so Linux 
should detect the broken cases.

-Andi
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