linux-kernel - Re: [PATCH] trim memory not covered by WB MTRRs

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Message-ID: <86802c440706260854w302df509xdba86f29989a5783@mail.gmail.com>
Date:	Tue, 26 Jun 2007 08:54:56 -0700
From:	"Yinghai Lu" <yhlu.kernel@...il.com>
To:	"Andi Kleen" <andi@...stfloor.org>
Cc:	"Eric W. Biederman" <ebiederm@...ssion.com>,
	"Jesse Barnes" <jesse.barnes@...el.com>,
	linux-kernel@...r.kernel.org, akpm@...ux-foundation.org,
	"Justin Piszcz" <jpiszcz@...idpixels.com>
Subject: Re: [PATCH] trim memory not covered by WB MTRRs

On 6/26/07, Andi Kleen <andi@...stfloor.org> wrote:
> > For the K7 and K8 cores AMD systems are exactly like Intel systems
> > with respect to MTRRs (although AMD systems also have additional registers)
> > For the K9 core (i.e. AMD socket F or the K8 with DDR2 support) there
>
> It's called K8RevE, not K9

For K8 Rev F and later, if you are using TOM2, cpu will assume the mem
between 4G and TOM2 is WB.

I think rule could be:
scan the var mtrrs to find out if there is any mtrr is used for 4G
above is set to WB, if it is true, will use trimming tricks.

YH
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