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Message-ID: <5FD5754DDBA0B1499B5A0B4BB5419485015CC9E1@fmsmsx411.amr.corp.intel.com>
Date: Fri, 6 Jul 2007 13:57:03 -0700
From: "Li, Tong N" <tong.n.li@...el.com>
To: "Andi Kleen" <andi@...stfloor.org>
Cc: "Andrew Morton" <akpm@...ux-foundation.org>,
"Mathieu Desnoyers" <mathieu.desnoyers@...ymtl.ca>,
"Alexey Dobriyan" <adobriyan@...il.com>,
<linux-kernel@...r.kernel.org>
Subject: RE: [patch 10/10] Scheduler profiling - Use immediate values
> I found that memory latency is difficult to measure in modern x86
> CPUs because they have very clever prefetchers that can often
> outwit benchmarks.
A pointer-chasing program that accesses a random sequence of addresses
usually can produce a good estimate on memory latency. Also, prefetching
can be turned off in BIOS or by modifying the MSRs.
> Another trap on P4 is that RDTSC is actually quite slow and
synchronizes
> the CPU; that can add large measurement errors.
>
> -Andi
The cost can be amortized if the portion of memory accesses is long
enough.
tong
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