linux-kernel - Re: ICH8 CF timeout (regression)...

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Date:	Mon, 6 Aug 2007 10:28:36 -0700
From:	Kristen Carlson Accardi <kristen.c.accardi@...el.com>
To:	Tejun Heo <htejun@...il.com>
Cc:	Daniel J Blueman <daniel.blueman@...il.com>,
	Mark Lord <lkml@....ca>, jgarzik@...ox.com,
	linux-ide@...r.kernel.org,
	Linux Kernel <linux-kernel@...r.kernel.org>
Subject: Re: ICH8 CF timeout (regression)...

On Sat, 04 Aug 2007 15:04:54 +0900
Tejun Heo <htejun@...il.com> wrote:

> Daniel J Blueman wrote:
> > Tejun,
> > 
> > On 03/08/07, Tejun Heo <htejun@...il.com> wrote:
> >> Daniel J Blueman wrote:
> >>> The ICH8 south-bridge I have is the mobile variant and does come
> >>> equipped with native parallel IDE - see page 447:
> >>> http://download.intel.com/design/chipsets/datashts/31305603.pdf . I do
> >>> see 35MB/s with DMA enabled from my CF on the 1 in 15 times the
> >>> libata-kernel does work.
> >>>
> >>> I can dump off and decode the configuration registers for the timing
> >>> and bus master registers in the working and non-working libata cases,
> >>> and the legacy ATA working case and see what's different.
> >> Does the attached patch change anything?
> > 
> > This addresses the issue 100%!
> > 
> > Due to the differences between the ICH8 non-mobile and mobile
> > variants, I've cooked the change into a new initialisation structure
> > for the ICH8M in the attached patch, if that helps at all.
> > 
> > The changes thus affect (correct) behaviour on the ICH8M in IDE mode
> > only...so should be safe for inclusion. There may be a similar
> > situation with ICH9Ms also.
> 
> [cc'ing Kristen, hello]
> 
> I think [P0 P2 IDE IDE] is correct for MAP 01b but can't find anything
> about it in the datasheet or spec update.  Kristen, can you please
> verify this.  The following bug is also fixed by using [P0 P2 IDE IDE].
> 
> http://bugzilla.kernel.org/show_bug.cgi?id=8809
> 
> Thanks.
> 
> -- 
> tejun
> 

In the data sheet in section 5.15.2.3 it describes a value of map.mv of
1 as meaning that the SATA controller is emulating the logical secondary
channel, and the PATA channel will be the primary.  For a value of
map.mv == 2, we have the SATA controller being primary, and the PATA
is secondary.  So, if I'm understanding the way ata_piix does mapping, 
it seems like for a value of 2, we should have [p0, p2, ide, ide] and 
for a value of 1 we should have [ide, ide, p0, p2] - although for ICH8M 
it seems like 1 should not be a valid value. My reading the ICH8 spec is 
that ICH8M only implements a map value of 2, and 1 should be reserved 
(see section 12.1.33).
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