[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <46B75C0E.8010007@gmail.com>
Date: Tue, 07 Aug 2007 02:36:14 +0900
From: Tejun Heo <htejun@...il.com>
To: Kristen Carlson Accardi <kristen.c.accardi@...el.com>
CC: Daniel J Blueman <daniel.blueman@...il.com>,
Mark Lord <lkml@....ca>, jgarzik@...ox.com,
linux-ide@...r.kernel.org,
Linux Kernel <linux-kernel@...r.kernel.org>
Subject: Re: ICH8 CF timeout (regression)...
Kristen Carlson Accardi wrote:
> In the data sheet in section 5.15.2.3 it describes a value of map.mv of
> 1 as meaning that the SATA controller is emulating the logical secondary
> channel, and the PATA channel will be the primary. For a value of
> map.mv == 2, we have the SATA controller being primary, and the PATA
> is secondary. So, if I'm understanding the way ata_piix does mapping,
> it seems like for a value of 2, we should have [p0, p2, ide, ide] and
> for a value of 1 we should have [ide, ide, p0, p2] - although for ICH8M
> it seems like 1 should not be a valid value. My reading the ICH8 spec is
> that ICH8M only implements a map value of 2, and 1 should be reserved
> (see section 12.1.33).
Alright, thanks a lot.
--
tejun
-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Powered by blists - more mailing lists