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Message-ID: <4714DBD7.7080706@zytor.com> Date: Tue, 16 Oct 2007 08:42:15 -0700 From: "H. Peter Anvin" <hpa@...or.com> To: Mikulas Patocka <mikulas@...ax.karlin.mff.cuni.cz> CC: Arjan van de Ven <arjan@...radead.org>, Nick Piggin <npiggin@...e.de>, Linux Kernel Mailing List <linux-kernel@...r.kernel.org> Subject: Re: LFENCE instruction Mikulas Patocka wrote: > On Mon, 15 Oct 2007, H. Peter Anvin wrote: > >> Mikulas Patocka wrote: >>> I know about unordered stores (movnti & similar) --- they basically use >>> write-combining method on memory that is normally write-back --- and they >>> need sfence. But which one instruction does unordered load and needs >>> lefence? >>> >> PREFETCHNTA. > > PREFETCH* doesn't change program semantics. The processor is allowed to > ignore prefetch instruction if it doesn't have resources needed for > prefetch. It not ordered wrt. fences. > > PREFETCHNTA was implemented as prefetch into L1 cache and omitting L2 > cache on Pentium 3 and M --- and it is implemented as prefetch into L2 > cache on other --- do it doesn't really use any special buffers. > It's semantics allows it to, though. It's not clear to me whether it is actually necessary on existing chips. It does, I believe, way-restricted prefetch on existing silicon. -hpa - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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