linux-kernel - Re: x86_64 and AMD with C1E

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Message-ID: <471FBC09.8050201@redhat.com>
Date:	Wed, 24 Oct 2007 17:41:29 -0400
From:	Chuck Ebbert <cebbert@...hat.com>
To:	Mikhail Kshevetskiy <mikhail.kshevetskiy@...il.com>
CC:	linux-kernel@...r.kernel.org, Thomas Gleixner <tglx@...utronix.de>
Subject: Re: x86_64 and AMD with C1E

On 10/24/2007 05:26 PM, Mikhail Kshevetskiy wrote:
>>>
>>> I fill something wrong here.
>>> Is it possible to reduce the amount of timer interrupts?
>>> Is it possible to force enable C1,C2 and C3 states when c1e disabled?
>>>
>> How are you disabling C1E?
>>
>>
> dirty hack, i just follow the FreeBSD way and clear C1e bit in lapic
> initialization code. I make it for test purpose only, so i do not produce a
> patch.
> 

Why does disabling C1E disable C1, C2 and C3?

Thomas, in the case of the machines where C1E is disabled on CPU 0 but
enabled on CPU 1, could we just disable it? Maybe it's a BIOS bug and the
vendor just forgot to disable CPU 1...
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