linux-kernel - Re: x86_64 and AMD with C1E

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Message-ID: <alpine.LFD.0.9999.0710250007230.3186@localhost.localdomain>
Date:	Thu, 25 Oct 2007 00:12:42 +0200 (CEST)
From:	Thomas Gleixner <tglx@...utronix.de>
To:	Chuck Ebbert <cebbert@...hat.com>
cc:	Mikhail Kshevetskiy <mikhail.kshevetskiy@...il.com>,
	linux-kernel@...r.kernel.org
Subject: Re: x86_64 and AMD with C1E

On Wed, 24 Oct 2007, Chuck Ebbert wrote:
> On 10/24/2007 05:26 PM, Mikhail Kshevetskiy wrote:
> >>>
> >>> I fill something wrong here.
> >>> Is it possible to reduce the amount of timer interrupts?
> >>> Is it possible to force enable C1,C2 and C3 states when c1e disabled?
> >>>
> >> How are you disabling C1E?
> >>
> >>
> > dirty hack, i just follow the FreeBSD way and clear C1e bit in lapic
> > initialization code. I make it for test purpose only, so i do not produce a
> > patch.
> > 
> 
> Why does disabling C1E disable C1, C2 and C3?
> 
> Thomas, in the case of the machines where C1E is disabled on CPU 0 but
> enabled on CPU 1, could we just disable it? Maybe it's a BIOS bug and the
> vendor just forgot to disable CPU 1...

It's definitely a BIOS bug and I doubt that disabling the bit works on
every BIOS. I have a system here on my desk, where neither of the CPUs
has the bit set, but the lapic timer stops wreckage is there once both
CPUs go into idle. 

The mindless creativity of BIOS writers seems to exceed the ability of
hardware designers to produce strange chips by orders of magnitude.

   tglx

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