linux-kernel - Re: [PATCH] x86: Voluntary leave

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Date:	Thu, 20 Dec 2007 14:28:03 -0500
From:	Len Brown <lenb@...nel.org>
To:	"H. Peter Anvin" <hpa@...or.com>
Cc:	Arjan van de Ven <arjan@...radead.org>,
	Ingo Molnar <mingo@...e.hu>,
	Venki Pallipadi <venkatesh.pallipadi@...el.com>,
	Thomas Gleixner <tglx@...utronix.de>,
	linux-kernel <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] x86: Voluntary leave_mm before entering ACPI C3

On Thursday 20 December 2007 11:16, H. Peter Anvin wrote:
> Arjan van de Ven wrote:
> > On Wed, 19 Dec 2007 11:48:14 -0800
> > "H. Peter Anvin" <hpa@...or.com> wrote:
> > 
> >> I think C3 guarantees that the cache contents stay intact, and thus
> >> it might make sense in some technology to preserve the TLB as well
> >> (being a kind of cache.)
> > 
> > that sounds nice. It's fiction though ;-)
> > 
> > The thing to realize is that linux only sees "ACPI C3";
> > the BIOS maps that C3 to..
> > well any of the C states the processor in the system has.
> > What you're saying is afaik correct for the *hardware* C3, not for the "C3" that Linux sees..   
> 
> Well, it can only map ACPI C3 to a state which is no more "dead" than 
> what would normally be permitted by C3.  IIRC, C3 is allowed to require 
> that DMA be turned off (unlike C2), but is not allowed to lose the CPU 
> state.

Re: mapping HW to ACPI C-states.

Right, it is fair game for the BIOS to map a "shallower" hardware C-state
to a "deeper" ACPI C-state.

Re: CPU state

All C-states preserve the CPU SW programming state.
(eg. while it may be saved and restored in HW,
 it appears to SW to be always intact).

Re: C3 guarantees that the cache contents stay intact

This is both true and false, depending on how you use the word "intact".

If "intact" == "stays valid in cache", then no, this not guaranteed.
The HW reserves the right to flush some or all of the L1 and L2
caches whenever it wants to --
this includes both HW and ACPI C2 and C3 states.

If "intact" = "cache consistent", then yes, this guarantee is true.
The way the guarantee is implemented varies by generation.
Older systems would lock the bus in C3 to assure
the processor was woken up for DMA to snoop.
Newer hardware simply wakes the cache to snoop
without waking the cores, or if it flushes the caches
then it doesn't have to snoop at all -- which also
counts as "cache consistent":-)

cheers,
-Len

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