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Message-ID: <47797E39.7090208@zytor.com>
Date:	Mon, 31 Dec 2007 15:41:45 -0800
From:	"H. Peter Anvin" <hpa@...or.com>
To:	Alan Cox <alan@...rguk.ukuu.org.uk>
CC:	Ondrej Zary <linux@...nbow-software.org>,
	Rene Herman <rene.herman@...access.nl>,
	Ingo Molnar <mingo@...e.hu>,
	Linus Torvalds <torvalds@...ux-foundation.org>,
	dpreed@...d.com, Islam Amer <pharon@...il.com>,
	Pavel Machek <pavel@....cz>, Ingo Molnar <mingo@...hat.com>,
	Andi Kleen <andi@...stfloor.org>,
	Thomas Gleixner <tglx@...utronix.de>,
	Linux Kernel <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] x86: provide a DMI based port 0x80 I/O delay override

Alan Cox wrote:
>> However, assuming a bus clock of 6 MHz should be safe (167 ns).
> 
> Agreed - or ISA timings directly. Boxes using WD80x3 are not going to
> have a TSC so might as well stick with port 0x80 as they have done just
> fine for the past 15 years.
> 
>> None of this really helps with *memory-mapped* 8390, though, since 
>> memory mapped writes can be posted.  Putting any IOIO transaction in the 
> 
> ISA isn't posted only PCI.
> 
> PCI 8390 clones seem to be a mix of ASICs and 8390x chips with
> some quite disgusting FPGA glue logic.
> 

ISA isn't posted no, but on several chipsets the upstream PCI bus will 
post MMIO writes to ISA space regardless of the spec.

	-hpa
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