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Message-Id: <1199425898.7291.30.camel@pasglop>
Date:	Fri, 04 Jan 2008 16:51:38 +1100
From:	Benjamin Herrenschmidt <benh@...nel.crashing.org>
To:	Robert Hancock <hancockr@...w.ca>
Cc:	Mark Lord <liml@....ca>, Allen Martin <AMartin@...dia.com>,
	Jeff Garzik <jeff@...zik.org>, Tejun Heo <htejun@...il.com>,
	Gabor Gombas <gombasg@...aki.hu>, linux-kernel@...r.kernel.org,
	linux-ide@...r.kernel.org, Kuan Luo <kluo@...dia.com>,
	Peer Chen <pchen@...dia.com>
Subject: Re: sata_nv + ADMA + Samsung disk problem


On Thu, 2008-01-03 at 19:43 -0600, Robert Hancock wrote:
> Benjamin Herrenschmidt wrote:
> >> Another thing about the PacDigi core:  one has to be very careful
> >> to avoid sequential accesses to sequential PCI locations when
> >> programming the chip -- it cannot handle merged register writes.
> >>
> >> So for any group of sequentially laid out registers, the code has
> >> to ensure it never writes two adjacent registers in sequence..
> > 
> > Ugh ? Write combining isn't permitted on normal registers afaik...
> > 
> > Ben.
> 
> Byte merging can be done by the chipset on MMIO writes (merging multiple 
> 8 or 16-bit writes into a single 32-bit cycle).

That is true, if they are consecutive. You mean that this HW is f*cked
up enough to actually have separate 8/16 bits registers that are
contiguous ? Yuck... I'm afraid you -have- to add reads in between to
guarantee that no merging will occur.

Cheers,

Ben.


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