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Message-ID: <20080111091841.04eecd54@laptopd505.fenrus.org>
Date: Fri, 11 Jan 2008 09:18:41 -0800
From: Arjan van de Ven <arjan@...radead.org>
To: dean gaudet <dean@...tic.org>
Cc: Ingo Molnar <mingo@...e.hu>, Andi Kleen <ak@...e.de>,
linux-kernel@...r.kernel.org, Thomas Gleixner <tglx@...utronix.de>,
"H. Peter Anvin" <hpa@...or.com>,
Venki Pallipadi <venkatesh.pallipadi@...el.com>,
suresh.b.siddha@...el.com, Dave Jones <davej@...hat.com>
Subject: Re: CPA patchset
On Fri, 11 Jan 2008 09:02:46 -0800 (PST)
dean gaudet <dean@...tic.org> wrote:
> > Bulk ops (string ops, etc.) will do full cacheline writes too,
> > without filling in the cacheline.
>
> on intel with fast strings enabled yes. mind you intel gives hints in
> the documentation these operations don't respect coherence... and i
> asked about this when they posted their memory ordering paper but got
> no response.
I know there's an answer on the way; it just needs to get checked by
architects for cpus we shipped in like the last 10 years ;)
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