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Message-ID: <C3BF420A.12CFE%Keir.Fraser@cl.cam.ac.uk>
Date: Fri, 25 Jan 2008 07:36:42 +0000
From: Keir Fraser <Keir.Fraser@...cam.ac.uk>
To: Jeremy Fitzhardinge <jeremy@...p.org>,
Nick Piggin <nickpiggin@...oo.com.au>
CC: Matt Mackall <mpm@...enic.com>,
Harvey Harrison <harvey.harrison@...il.com>,
Ingo Molnar <mingo@...e.hu>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Andi Kleen <ak@...e.de>, Jan Beulich <jbeulich@...ell.com>
Subject: Re: [PATCH UPDATE] x86: ignore spurious faults
On 25/1/08 00:26, "Jeremy Fitzhardinge" <jeremy@...p.org> wrote:
>> I (obviously) don't know exactly how the TLB works in x86, but I
>> thought that on a miss, the CPU walks the pagetables first before
>> faulting? Maybe that's not the case if there is an RO entry
>> actually in the TLB?
>>
>
> My understanding is that it will fault immediately if there's a TLB
> entry, and rewalk the tables on return from the fault before restarting
> the instruction, so there's no need for an explicit TLB flush. The TLB
> doesn't have a notion of negative cache entries, so any entry represents
> a present page of some variety.
Yes, write access with a r/o TLB entry causes the TLB entry to be flushed
and an immediate #PF with no page walk. This is a hardware optimisation for
copy-on-write demand faults. Both Intel and AMD implement it.
-- Keir
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