lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <47992CB2.8050606@goop.org>
Date:	Thu, 24 Jan 2008 16:26:26 -0800
From:	Jeremy Fitzhardinge <jeremy@...p.org>
To:	Nick Piggin <nickpiggin@...oo.com.au>
CC:	Matt Mackall <mpm@...enic.com>,
	Harvey Harrison <harvey.harrison@...il.com>,
	Ingo Molnar <mingo@...e.hu>,
	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
	Andi Kleen <ak@...e.de>,
	Keir Fraser <Keir.Fraser@...cam.ac.uk>,
	Jan Beulich <jbeulich@...ell.com>
Subject: Re: [PATCH UPDATE] x86: ignore spurious faults

Nick Piggin wrote:
> On Friday 25 January 2008 06:21, Jeremy Fitzhardinge wrote:
>   
>> Matt Mackall wrote:
>>     
>>> There's perhaps an opportunity to do this lazy TLB trick in the mmap
>>> path as well, where RW mappings are initially mapped as RO so we can
>>> catch processes dirtying them and then switched to RW. If the mapping is
>>> shared across threads on multiple cores, we can defer synchronizing the
>>> TLBs on the others.
>>>       
>> I think spurious usermode faults are already dealt with.
>> handle_pte_fault() does essentially the same thing as this patch:
>>
>> 	if (ptep_set_access_flags(vma, address, pte, entry, write_access)) {
>> 		update_mmu_cache(vma, address, entry);
>> 	} else {
>> 		/*
>> 		 * This is needed only for protection faults but the arch code
>> 		 * is not yet telling us if this is a protection fault or not.
>> 		 * This still avoids useless tlb flushes for .text page faults
>> 		 * with threads.
>> 		 */
>> 		if (write_access)
>> 			flush_tlb_page(vma, address);
>> 	}
>>     
>
> I (obviously) don't know exactly how the TLB works in x86, but I
> thought that on a miss, the CPU walks the pagetables first before
> faulting? Maybe that's not the case if there is an RO entry
> actually in the TLB?
>   

My understanding is that it will fault immediately if there's a TLB 
entry, and rewalk the tables on return from the fault before restarting 
the instruction, so there's no need for an explicit TLB flush.  The TLB 
doesn't have a notion of negative cache entries, so any entry represents 
a present page of some variety.

    J
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ