linux-kernel - Re: [PATCH 11 of 11] x86: defer cr3 reload when doing pud

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Message-ID: <C3C0235A.12D8E%Keir.Fraser@cl.cam.ac.uk>
Date:	Fri, 25 Jan 2008 23:38:02 +0000
From:	Keir Fraser <Keir.Fraser@...cam.ac.uk>
To:	Jeremy Fitzhardinge <jeremy@...p.org>,
	"H. Peter Anvin" <hpa@...or.com>
CC:	Ingo Molnar <mingo@...e.hu>, LKML <linux-kernel@...r.kernel.org>,
	Andi Kleen <ak@...e.de>, Jan Beulich <jbeulich@...ell.com>,
	Eduardo Pereira Habkost <ehabkost@...hat.com>,
	Ian Campbell <ijc@...lion.org.uk>,
	William Irwin <wli@...omorphy.com>,
	Linus Torvalds <torvalds@...ux-foundation.org>
Subject: Re: [PATCH 11 of 11] x86: defer cr3 reload when doing pud_clear()

On 25/1/08 22:54, "Jeremy Fitzhardinge" <jeremy@...p.org> wrote:

> The only possibly relevant comment I can find in vol3a is:
> 
>     Older IA-32 processors that implement the PAE mechanism use uncached
>     accesses when loading page-directory-pointer table entries. This
>     behavior is
>     model specific and not architectural. More recent IA-32 processors may
>     cache page-directory-pointer table entries.

Go read the Intel application note "TLBs, Paging-Structure Caches, and Their
Invalidation" at http://www.intel.com/design/processor/applnots/317080.pdf

Section 8.1 explains about the PDPTR cache in 32-bit PAE mode, which can
only be refreshed by appropriate tickling of CR0, CR3 or CR4.

It is also important to note that *any* valid page directory entry at *any*
level in the page-table hierarchy can become cached at *any* time. Basically
TLB lookup is performed as a longest-prefix match on the linear address to
skip as many levels in a page-table walk as possible (where a walk is
needed, because there is no full-length match on the linear address). So, if
you modify a directory entry from present to not-present, or change the page
directory that a valid pde points to, you probably need to flush the pde
caching structure. One piece of good news is that all pde caches are flushed
by any arbitrary INVLPG.

 -- Keir

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