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Message-ID: <4814FAA0.8060705@zytor.com>
Date: Sun, 27 Apr 2008 15:13:52 -0700
From: "H. Peter Anvin" <hpa@...or.com>
To: James Bottomley <James.Bottomley@...senPartnership.com>
CC: Ingo Molnar <mingo@...e.hu>, Thomas Gleixner <tglx@...utronix.de>,
linux-kernel <linux-kernel@...r.kernel.org>
Subject: Re: Breakage caused by unreviewed patch in x86 tree
James Bottomley wrote:
> On Sun, 2008-04-27 at 15:00 -0700, H. Peter Anvin wrote:
>> James Bottomley wrote:
>>> I might add that the intel SAPIC functions
>>> in roughly the same manner, so this might break more than just voyager.
>> Are you referring to the IA64 SAPIC here, or something else? The only
>> mention of SAPIC in the x86 tree appear to be naming of fields in ACPI
>> tables.
>
> Yes, that's the one ... but I believe a class of the xAPICs also used a
> similar principle.
I certainly have never seen a system on which the APIC has been mapped
cacheable. I would be very interested in the details, so if you could
elaborate that would be extremely useful.
-hpa
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