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Message-Id: <1209334729.3801.75.camel@localhost.localdomain> Date: Sun, 27 Apr 2008 18:18:49 -0400 From: James Bottomley <James.Bottomley@...senPartnership.com> To: "H. Peter Anvin" <hpa@...or.com> Cc: Ingo Molnar <mingo@...e.hu>, Thomas Gleixner <tglx@...utronix.de>, linux-kernel <linux-kernel@...r.kernel.org> Subject: Re: Breakage caused by unreviewed patch in x86 tree On Sun, 2008-04-27 at 15:13 -0700, H. Peter Anvin wrote: > James Bottomley wrote: > > On Sun, 2008-04-27 at 15:00 -0700, H. Peter Anvin wrote: > >> James Bottomley wrote: > >>> I might add that the intel SAPIC functions > >>> in roughly the same manner, so this might break more than just voyager. > >> Are you referring to the IA64 SAPIC here, or something else? The only > >> mention of SAPIC in the x86 tree appear to be naming of fields in ACPI > >> tables. > > > > Yes, that's the one ... but I believe a class of the xAPICs also used a > > similar principle. > > I certainly have never seen a system on which the APIC has been mapped > cacheable. I would be very interested in the details, so if you could > elaborate that would be extremely useful. Not really ... I just remember when the SAPIC and later the xAPIC details were published as novel nearly a decade ago, I remember saying that some of the voyager interrupt controllers had been using a similar method for years. James -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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