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Message-ID: <86802c440804281941h440c7a86kd86fd4d9dcf91ad4@mail.gmail.com>
Date: Mon, 28 Apr 2008 19:41:43 -0700
From: "Yinghai Lu" <yhlu.kernel@...il.com>
To: "Gabriel C" <nix.or.die@...glemail.com>
Cc: "Mika Fischer" <mika.fischer@...pnet.de>,
"Ingo Molnar" <mingo@...e.hu>,
"Andrew Morton" <akpm@...ux-foundation.org>,
"H. Peter Anvin" <hpa@...or.com>,
LKML <linux-kernel@...r.kernel.org>,
"Jesse Barnes" <jesse.barnes@...el.com>, balajirrao@...il.com,
"Andi Kleen" <andi@...stfloor.org>,
"Thomas Gleixner" <tglx@...utronix.de>
Subject: Re: [PATCH] x86_32: trim memory by updating e820 v3
On Mon, Apr 28, 2008 at 6:05 PM, Gabriel C <nix.or.die@...glemail.com> wrote:
>
> Yinghai Lu wrote:
> > On Mon, Apr 28, 2008 at 3:56 PM, Gabriel C <nix.or.die@...glemail.com> wrote:
> >> Yinghai Lu wrote:
> >> > On Mon, Apr 28, 2008 at 2:19 PM, Gabriel C <nix.or.die@...glemail.com> wrote:
> >> >> Gabriel C wrote:
> >> >> > Gabriel C wrote:
> >> >> >> Yinghai Lu wrote:
> >> >> >>> On Mon, Apr 28, 2008 at 7:24 AM, Gabriel C <nix.or.die@...glemail.com> wrote:
> >> >> >>>> Mika Fischer wrote:
> >> >> >>>> > Hi Ingo,
> >> >> >>>> >
> >> >> >>>> > I'm having the same problem.
> >> >> >>>> >
> >> >> >>>> > Ingo Molnar schrieb:
> >> >> >>>> >> excellent. So just to make sure: this box never had proper graphics
> >> >> >>>> >> under Linux (under no previous kernel), due to the way the BIOS has set
> >> >> >>>> >> up the MTRR's, right?
> >> >> >>>> >
> >> >> >>>> > Well, not quite. X still works fine, but since the video memory is
> >> >> >>>> > overlapped by two of the existing MTRRs, X cannot add a write-combining
> >> >> >>>> > range for the video memory. That makes X rather slow especially if you
> >> >> >>>> > use DRI for Compiz etc.
> >> >> >>>>
> >> >> >>>> Well you are lucky then :)
> >> >> >>>>
> >> >> >>>> Yeah X 'worked' but it worked as slow as with vesa video driver here.
> >> >> >>> [ 0.000000] rangeX: 0000000000000000 - 00000000d0000000
> >> >> >>> [ 0.000000] Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB
> >> >> >>> [ 0.000000] Setting variable MTRR 1, base: 2048MB, range: 1024MB, type WB
> >> >> >>> [ 0.000000] Setting variable MTRR 2, base: 3072MB, range: 256MB, type WB
> >> >> >>> [ 0.000000] range0: 00000000cf800000 - 00000000cf800000
> >> >> >>> [ 0.000000] range: 00000000cf800000 - 00000000d0000000
> >> >> >>> [ 0.000000] Setting variable MTRR 3, base: 3320MB, range: 8MB, type WB
> >> >> >>> [ 0.000000] range0: 0000000100000000 - 0000000120000000
> >> >> >>> [ 0.000000] Setting variable MTRR 4, base: 4096MB, range: 512MB, type WB
> >> >> >>> [ 0.000000] range: 0000000120000000 - 0000000130000000
> >> >> >>> [ 0.000000] Setting variable MTRR 5, base: 4608MB, range: 256MB, type WB
> >> >> >>> [ 0.000000] hole: 000000012c000000 - 0000000130000000
> >> >> >>> [ 0.000000] Setting variable MTRR 6, base: 4800MB, range: 64MB, type UC
> >> >> >>>
> >> >> >>> so your X server need two entries for WB?
> >> >> >>>
> >> >> >>> can you send out /proc/mtrr with booting with disable_mtrr_cleanup?
> >> >> >> I can just not right now , cannot reboot the box yet. In about 1h or so , maybe less.
> >> >> >
> >> >> > Here the output with v3 which is disabled by default:
> >> >> >
> >> >> > --($:~)-- cat /proc/mtrr
> >> >> > reg00: base=0xd0000000 (3328MB), size= 256MB: uncachable, count=1
> >> >> > reg01: base=0xe0000000 (3584MB), size= 512MB: uncachable, count=1
> >> >> > reg02: base=0x00000000 ( 0MB), size=4096MB: write-back, count=1
> >> >> > reg03: base=0x100000000 (4096MB), size= 512MB: write-back, count=1
> >> >> > reg04: base=0x120000000 (4608MB), size= 128MB: write-back, count=1
> >> >> > reg05: base=0x128000000 (4736MB), size= 64MB: write-back, count=1
> >> >> > reg06: base=0xcf600000 (3318MB), size= 2MB: uncachable, count=1
> >> >> >
> >> >> > dmesg is saying now :
> >> >> >
> >> >> > [ 22.764595] mtrr: type mismatch for d0000000,10000000 old: write-back new: write-combining
> >> >> >
> >> >> >
> >> >> > My card settings in BIOS ( that was default ) are the following :
> >> >> >
> >> >> > DVMT Mode -> DVMT Mode ( possible setting DVMT Mode or Fixed Mode )
> >> >> > DVMT / Memory -> 256MB ( possible settings 128/256 MB or Maximum DVMT )
> >> >> >
> >> >> > Initiate Graphics Adapter -> PEG/PCI ( possible settings IGD , PCI/IGD , PCI/PEG , PEG/IGD )
> >> >> > Internal Graphics Mode Select -> Enabled,8MB ( possible settings Enabled,8MB , Enabled,1MB maybe Disabled I forgot to look)
> >> >> > PEG Port -> Auto ( possible settings Auto , Disabled )
> >> >> > PEG Port Force x1 -> Disabled ( possible settings Enabled , Disabled )
> >> >> >
> >> >> > Of course these settings are only possible when the card is not disabled :)
> >> >> >
> >> >> > I'm gonna try v4 now and enable it. Please let me know if you need more infos.
> >> >>
> >> >> Hmm v4 doesn't work anymore here ( I've tested with all possible settings in BIOS ).
> >> >> It takes 6 minutes to boot to :
> >> >>
> >> >
> >> > so you card is using 256M and 8M? 0xd0000000-0xe0000000, where is
> >> > another 8M address.
> >>
> >> Looks like this , yes. Is using the 256MB Memory and the 8MB for Graphics Mode Select.
> >>
> >> I'm not really sure why the 8MB are needed , BIOS book doesn't tell me.
> >> I could try to disable and see what I get =)
> >>
> >>
> >>
> >> >
> >> > mtrr by BIOS is very interesting:
> >> > before
> >> >> > reg02: base=0x00000000 ( 0MB), size=4096MB: write-back, count=1
> >> >> > reg06: base=0xcf600000 (3318MB), size= 2MB: uncachable, count=1
> >> >> > reg00: base=0xd0000000 (3328MB), size= 256MB: uncachable, count=1
> >> >> > reg01: base=0xe0000000 (3584MB), size= 512MB: uncachable, count=1
> >> >> > reg03: base=0x100000000 (4096MB), size= 512MB: write-back, count=1
> >> >> > reg04: base=0x120000000 (4608MB), size= 128MB: write-back, count=1
> >> >> > reg05: base=0x128000000 (4736MB), size= 64MB: write-back, count=1
> >> >
> >> >
> >> > after 256M chunk size got
> >> >> >>> [ 0.000000] Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB
> >> >> >>> [ 0.000000] Setting variable MTRR 1, base: 2048MB, range: 1024MB, type WB
> >> >> >>> [ 0.000000] Setting variable MTRR 2, base: 3072MB, range: 256MB, type WB
> >> >> >>> [ 0.000000] Setting variable MTRR 3, base: 3320MB, range: 8MB, type WB
> >> >> >>> [ 0.000000] Setting variable MTRR 4, base: 4096MB, range: 512MB, type WB
> >> >> >>> [ 0.000000] Setting variable MTRR 5, base: 4608MB, range: 256MB, type WB
> >> >> >>> [ 0.000000] Setting variable MTRR 6, base: 4800MB, range: 64MB, type UC
> >> >
> >> > so the convering is right..., need to spare another entry for your card.
> >> >
> >> > or we can dumping the
> >> >> >>> [ 0.000000] Setting variable MTRR 3, base: 3320MB, range: 8MB, type WB
> >> > for extra entra...
> >> >
> >> > but the mtrr trimming code need to be updated instead of only using highest_pfn
> >> >
> >> > YH
> >> >
> >
> > please try to test patch with mtrr_chunk_size= 2g; 1g, 512m, 128m. etc.
> > only for test: i comment out the fill_var_state..
>
> There are the dmesg's , down to 2m and without chunk_size :
>
> http://frugalware.org/~crazy/mtrr/mtrr/
please check this one v6 test.
please only check =2g, 1g, and 512m, 256m, 128m, 64m.
Thanks
Yinghai Lu
View attachment "mtrr_cleanup_v6.patch" of type "text/x-patch" (15910 bytes)
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