linux-kernel - Re: MMIO and gcc re-ordering issue

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Message-ID: <Pine.LNX.4.64.0805291442420.18832@t2.domain.actdsltmp>
Date:	Thu, 29 May 2008 14:48:28 -0700 (PDT)
From:	Trent Piepho <tpiepho@...escale.com>
To:	Benjamin Herrenschmidt <benh@...nel.crashing.org>
cc:	Jes Sorensen <jes@....com>, Roland Dreier <rdreier@...co.com>,
	Arjan van de Ven <arjan@...radead.org>,
	linux-arch@...r.kernel.org, linux-kernel@...r.kernel.org,
	linuxppc-dev@...abs.org, scottwood@...escale.com,
	torvalds@...ux-foundation.org, David Miller <davem@...emloft.net>,
	alan@...rguk.ukuu.org.uk
Subject: Re: MMIO and gcc re-ordering issue

On Fri, 30 May 2008, Benjamin Herrenschmidt wrote:
> On Thu, 2008-05-29 at 10:47 -0400, Jes Sorensen wrote:
> Interesting. I've always been taught by ia64 people that mmiowb() was
> intended to be used solely between writel() and spin_unlock().

That's what I gathered too, based on what's written in memory-barriers.txt,
which is the only kernel docs I could find that addressed this.

> Yes, this has some cost (can be fairly significant on powerpc too) but
> I think it's a very basic assumption from drivers that consecutive
> writel's, especially issued by the same CPU, will get to the device
> in order.

It's also what memory-barriers.txt says they should do.

> If this is a performance problem, then provide relaxed variants and
> use them in selected drivers.

I wrote a JTAG over gpio driver for the powerpc MPC8572DS platform.  With the
non-raw io accessors, the JTAG clock can run at almost ~9.5 MHz.  Using raw
versions (which I had to write since powerpc doesn't have any), the clock
speed increases to about 28 MHz.  So it can make a very significant different.
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