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Message-Id: <200805291453.38492.jbarnes@virtuousgeek.org>
Date: Thu, 29 May 2008 14:53:38 -0700
From: Jesse Barnes <jbarnes@...tuousgeek.org>
To: benh@...nel.crashing.org
Cc: Jes Sorensen <jes@....com>, Roland Dreier <rdreier@...co.com>,
Arjan van de Ven <arjan@...radead.org>,
linux-arch@...r.kernel.org, linux-kernel@...r.kernel.org,
tpiepho@...escale.com, linuxppc-dev@...abs.org,
scottwood@...escale.com, torvalds@...ux-foundation.org,
David Miller <davem@...emloft.net>, alan@...rguk.ukuu.org.uk
Subject: Re: MMIO and gcc re-ordering issue
On Thursday, May 29, 2008 2:40 pm Benjamin Herrenschmidt wrote:
> On Thu, 2008-05-29 at 10:47 -0400, Jes Sorensen wrote:
> > The only way to guarantee ordering in the above setup, is to either
> > make writel() fully ordered or adding the mmiowb()'s inbetween the two
> > writel's. On Altix you have to go and read from the PCI brige to
> > ensure all writes to it have been flushed, which is also what mmiowb()
> > is doing. If writel() was to guarantee this ordering, it would make
> > every writel() call extremely expensive :-(
>
> Interesting. I've always been taught by ia64 people that mmiowb() was
> intended to be used solely between writel() and spin_unlock().
Well, that *was* true, afaik, but maybe these days multipath isn't just for
fail-over. If that's true, then yeah making every single writeX ordered
would be the only way to go...
> If this is a performance problem, then provide relaxed variants and
> use them in selected drivers.
Sounds reasonable. That way drivers "just work" and important drivers can be
optimized.
Jesse
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