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Message-ID: <Pine.LNX.4.64.0806161928180.22820@schroedinger.engr.sgi.com>
Date: Mon, 16 Jun 2008 19:29:13 -0700 (PDT)
From: Christoph Lameter <clameter@....com>
To: Rusty Russell <rusty@...tcorp.com.au>
cc: Nick Piggin <nickpiggin@...oo.com.au>,
Martin Peschke <mp3@...ibm.com>,
Andrew Morton <akpm@...ux-foundation.org>,
linux-arch@...r.kernel.org, linux-kernel@...r.kernel.org,
David Miller <davem@...emloft.net>,
Eric Dumazet <dada1@...mosbay.com>,
Peter Zijlstra <peterz@...radead.org>,
Mike Travis <travis@....com>
Subject: Re: [patch 04/41] cpu ops: Core piece for generic atomic per cpu
operations
On Tue, 17 Jun 2008, Rusty Russell wrote:
> > The ia64 hook could simply return the address of percpu area that
> > was reserved when the per node memory layout was generated (which happens
> > very early during node bootstrap).
>
> Apologies, this time I read the code. I thought IA64 used the pinned TLB area
> to access per-cpu vars under some circumstances, but they only do that via an
> arch-specific macro.
>
> So creating new congruent mappings to expand the percpu area(s) is our main
> concern now?
The concern here was just consolidating the setup code for the per cpu
areas.
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