linux-kernel - Re: interrupt overhead on ARM architecture

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Date:	Tue, 29 Jul 2008 15:02:47 +1000
From:	Iwo Mergler <iwo@...l-direct.com.au>
To:	Alessio Sangalli <alesan@...oweb.com>
CC:	linux-kernel <linux-kernel@...r.kernel.org>
Subject: Re: interrupt overhead on ARM architecture

Alessio Sangalli wrote:
> Hi there, I was wondering if somebody ever did some measurements of the
> interrupt overhead, measured in clock cycles. Basically how much time it
> takes to do the context switch and reach the ISR, and back. My target is
> the ARM9...
> 
> Thanks
> Alessio
>
This depends very much on the system, both hardware and software.

The ARM9 processor can get from an active interrupt line to the
first instruction in the ISR in about 30 clock cycles.

However, it can take a multiple of that if the ISR and relevant
stacks are not in cache. On many systems this can cost you
a few hundred processor clocks, depending on what the software
did just before the interrupt.

At this point the OS ISR is running. It needs to find out which
hardware device triggered. The processor has only one interrupt
line (OK, two), but some systems have hundreds of interrupt sources.

Depending on the interrupt controller hardware, finding out which
interrupt fired, is a matter of reading one register in the best case.
Or reading several and searching for set bits in software in the
worst case. Again, a few tens of cycles, depending on the system
architecture.

Only then the OS ISR can actually call the driver's ISR, which
is probably what you are really interested in.

In other words, you can't even measure the latency on a particular
system and then assume it will stay anywhere near constant. Comparing
different systems with the same processor core is hopeless.

Kind regards,

Iwo

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