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Message-ID: <76780B19A496DC4B80439008DAD7076C0CF9E403@PDSMSX501.ccr.corp.intel.com>
Date:	Mon, 18 Aug 2008 14:19:36 +0800
From:	"Li, Shaohua" <shaohua.li@...el.com>
To:	Arjan van de Ven <arjan@...radead.org>
CC:	Ingo Molnar <mingo@...e.hu>, lkml <linux-kernel@...r.kernel.org>,
	"airlied@...ux.ie" <airlied@...ux.ie>,
	Andrew Morton <akpm@...ux-foundation.org>,
	Ingo Molnar <mingo@...hat.com>,
	"Siddha, Suresh B" <suresh.b.siddha@...el.com>,
	"Pallipadi, Venkatesh" <venkatesh.pallipadi@...el.com>,
	Thomas Gleixner <tglx@...utronix.de>,
	"H. Peter Anvin" <hpa@...or.com>
Subject: RE: [patch 2/2] reduce tlb/cache flush times of agpgart memory
 allocation



>-----Original Message-----
>From: Arjan van de Ven [mailto:arjan@...radead.org]
>Sent: Monday, August 18, 2008 11:57 AM
>To: Li, Shaohua
>Cc: Ingo Molnar; lkml; airlied@...ux.ie; Andrew Morton; Ingo Molnar; Siddha,
>Suresh B; Pallipadi, Venkatesh; Thomas Gleixner; H. Peter Anvin
>Subject: Re: [patch 2/2] reduce tlb/cache flush times of agpgart memory
>allocation
>
>On Mon, 18 Aug 2008 09:21:12 +0800
>"Li, Shaohua" <shaohua.li@...el.com> wrote:
>
>>
>> >
>> >it really needs something else instead; it needs airlied's array
>> >allocator
>> >otherwise you hit the second wall as well (the pat checks per page)
>> Somebody should have a measurement. In my test, the real bottleneck
>> is the cache flush. It appears flush cache page is slow if there are
>> a lot of pages, In my patch, I use a wbinvd. This can be optimized to
>> do wbinvd with a threshold. Maybe airlied can change his patch with
>> this way.
>
>
>it would be great if you had time to update his patch and this to
>it...
I'll do it soon.

>and the logic probably should be "if there's more than X pags in the
>the array, just use wbinvd".
>Although wbinvd is very painful if you have 12Mb of cache and you wipe
>it for all cores in the system ;-(
This might not be that bad, changing attribute isn't frequently used.

Thanks,
Shaohua
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