linux-kernel - RE: [PATCH] x86: Add clflush before monitor for Intel 7400 series

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Message-ID: <7E82351C108FA840AB1866AC776AEC4637B799FB@orsmsx505.amr.corp.intel.com>
Date:	Fri, 17 Oct 2008 13:51:42 -0700
From:	"Pallipadi, Venkatesh" <venkatesh.pallipadi@...el.com>
To:	"H. Peter Anvin" <hpa@...or.com>
CC:	Ingo Molnar <mingo@...e.hu>, Thomas Gleixner <tglx@...utronix.de>,
	linux-kernel <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH] x86: Add clflush before monitor for Intel 7400 series



>-----Original Message-----
>From: H. Peter Anvin [mailto:hpa@...or.com]
>Sent: Friday, October 17, 2008 1:13 PM
>To: Pallipadi, Venkatesh
>Cc: Ingo Molnar; Thomas Gleixner; linux-kernel
>Subject: Re: [PATCH] x86: Add clflush before monitor for Intel
>7400 series
>
>Pallipadi, Venkatesh wrote:
>>
>> hpa,
>>
>> Do you still have reservations about this being expensive.
>> Note that this is only done when a CPU is about to go idle and
>> The cost of clflush itself will be minimal compared to idle
>> entry + idle exit latency.
>>
>
>I guess I'm a bit confused about the tradeoff of CLFLUSH versus simply
>disabling MWAIT.  This is a relatively recent processor and so
>optimizing matters (if this was a P4 I would be more worried about what
>has least impact on the kernel as a whole.)

As of now this is only for a limited models of CPUs (MP CPUs)
and not a norm. It is a errata on this CPU and not
something that is going to become architectural.

>Entry and exit latency do matter (specifically, exit latency
>matters for
>longer waits and the combined entry+exit latency matters for
>short waits.)

Agreed. In this case the overhead of clflush is very low (~30 cycles)
and C1 entry+exit latency will be of the order of few hundreds of cycles for
fastest wakeup.

>On the other hand, perhaps what we need to do is to get the fix in and
>worry about performance later.
>
>        -hpa

Thanks,
Venki
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