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Message-ID: <20081030172515.GW31673@kernel.dk>
Date:	Thu, 30 Oct 2008 18:25:15 +0100
From:	Jens Axboe <jens.axboe@...cle.com>
To:	Suresh Siddha <suresh.b.siddha@...el.com>
Cc:	"paulmck@...ux.vnet.ibm.com" <paulmck@...ux.vnet.ibm.com>,
	"mingo@...e.hu" <mingo@...e.hu>,
	"jeremy.fitzhardinge@...rix.com" <jeremy.fitzhardinge@...rix.com>,
	"nickpiggin@...oo.com.au" <nickpiggin@...oo.com.au>,
	"torvalds@...ux-foundation.org" <torvalds@...ux-foundation.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"Mallick, Asit K" <asit.k.mallick@...el.com>
Subject: Re: [patch] generic-ipi: fix the smp_mb() placement

On Thu, Oct 30 2008, Suresh Siddha wrote:
> On Thu, Oct 30, 2008 at 12:20:30AM -0700, Jens Axboe wrote:
> > > @@ -76,6 +72,11 @@ static void generic_exec_single(int cpu, struct call_single_data *data)
> > >  	list_add_tail(&data->list, &dst->list);
> > >  	spin_unlock_irqrestore(&dst->lock, flags);
> > >  
> > > +	/*
> > > +	 * Make the list addition visible before sending the ipi.
> > > +	 */
> > > +	smp_mb();
> > > +
> > >  	if (ipi)
> > >  		arch_send_call_function_single_ipi(cpu);
> > 
> > We can downgrade this to a smp_wmb().
> 
> No. We want the ipi receiver to see the new consistent data rather
> than possible old consistent data.

Oh right, we need visibility here and not just store ordering.

> 
> And on x86, smp_wmb() is a simple barrier() (in !CONFIG_X86_OOSTORE)
> and which doesn't do much in this case.
> 
> on x86 mfence (smp_mb()) will ensure that msr based APIC (x2apic)
> accesses (ipi) will be visible only after the memory operations before
> smp_mb() are made visible.

OK, I'm convinced. I'll queue up the patch, thanks!

-- 
Jens Axboe

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