linux-kernel - Re: [PATCH] x86: Support always running TSC on Intel CPUs

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Message-ID: <20081117192629.664fc364@infradead.org>
Date:	Mon, 17 Nov 2008 19:26:29 -0800
From:	Arjan van de Ven <arjan@...radead.org>
To:	"H. Peter Anvin" <hpa@...or.com>
Cc:	Venki Pallipadi <venkatesh.pallipadi@...el.com>,
	Ingo Molnar <mingo@...e.hu>,
	Thomas Gleixner <tglx@...utronix.de>,
	linux-kernel <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] x86: Support always running TSC on Intel CPUs

On Mon, 17 Nov 2008 17:07:26 -0800
"H. Peter Anvin" <hpa@...or.com> wrote:

> Venki Pallipadi wrote:
> >>>
> >> I was under the impression that C2 was invoked by the chipset on a
> >> thermal condition, at least on older (P3-era) processors.  Is that
> >> no longer true?  If what you say is above (HLT and MWAIT only),
> >> then *was* it ever true?
> > 
> > I should also add io port based C-state to HLT and MWAIT. But, that
> > again is OS initiated.
> > 
> > I don't know of C2 invocation in thermal condition. Thermal
> > condition, all CPUs that I know of (P3 and beyond), use either
> > clock modulation or frequency changes. And on some such CPUs, where
> > TSC runs at constant freq during such modulation/freq change, we
> > set CONSTANT_TSC bit based on model number check. So, on CPUs
> > earlier than those, we cannot use TSC or we have to scale TSC based
> > on freq. This patch shouldn't have any impact for those CPUs.
> > 
> 
> I believe there are CPUs -- again, in the P3-era range at least --
> which invoke C2 from the chipset on thermal conditions (and basically
> PWM the CPU.)  I'd like to get that clarified so we don't trip up on
> that.

p3-era cpus didn't stop tsc in c2 afaik.


-- 
Arjan van de Ven 	Intel Open Source Technology Centre
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