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Message-ID: <20081127135026.GO6703@one.firstfloor.org>
Date:	Thu, 27 Nov 2008 14:50:26 +0100
From:	Andi Kleen <andi@...stfloor.org>
To:	Thomas Gleixner <tglx@...utronix.de>
Cc:	eranian@...il.com, Andi Kleen <andi@...stfloor.org>,
	David Miller <davem@...emloft.net>,
	linux-kernel@...r.kernel.org, akpm@...ux-foundation.org,
	mingo@...e.hu, x86@...nel.org, sfr@...b.auug.org.au
Subject: Re: [patch 05/24] perfmon: X86 generic code (x86)

On Thu, Nov 27, 2008 at 02:32:33PM +0100, Thomas Gleixner wrote:
> On Thu, 27 Nov 2008, stephane eranian wrote:
> > That's true for Intel.
> > On AMD64, I think you can get at most one sample out of a irq-off
> > region using IBS.
> 
> Exactly the same amount which you get with the NMI/self_IPI out of an
> irq-off region.

True. It would really need a NMI safe queue. 

-Andi

-- 
ak@...ux.intel.com
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