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Message-ID: <20081225001144.48423fea@lxorguk.ukuu.org.uk> Date: Thu, 25 Dec 2008 00:11:44 +0000 From: Alan Cox <alan@...rguk.ukuu.org.uk> To: Robert Hancock <hancockr@...w.ca> Cc: linux-kernel@...r.kernel.org, dhowells@...hat.com Subject: Re: Memory vs. MMIO ordering, again > What that documentation is suggesting is that MMIO writes to uncached > memory (what the normal mapping functions will give you) can pass > previous writes to cached memory. It doesn't indicate how this is to be > avoided, however. They can. How you avoid it depends upon the bus but the problem is really really rare as a corner case and almost the only device affected is graphics because nobody uses cached memory on the PCI bus except graphics cards and a couple of obscure other cases like I2O. The graphics people implement various fencing operations and they are generally tied down low level with AGP, GARTs and other places mere mortals (ie most people except the DRI team) should not tread ;) You need to distinguish between cachable memory remote on things like the PCI bus (eg frame buffers) which are your problem and cachable memory in the sense of main memory, which is handled by the pci_map functions or kept coherent if allocated via the PCI coherent memory allocator - in which case all you have to watch is the compiler and write buffers on the CPU. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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