linux-kernel - Re: [PATCH] x86: Remove readq()/writeq() on 32-bit

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Message-ID: <4A0B49C4.4000502@garzik.org>
Date:	Wed, 13 May 2009 18:29:24 -0400
From:	Jeff Garzik <jeff@...zik.org>
To:	Roland Dreier <rdreier@...co.com>
CC:	Hitoshi Mitake <h.mitake@...il.com>, Ingo Molnar <mingo@...e.hu>,
	David Miller <davem@...emloft.net>,
	Linus Torvalds <torvalds@...ux-foundation.org>, hpa@...or.com,
	tglx@...utronix.de, rpjday@...shcourse.ca,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH] x86: Remove readq()/writeq() on 32-bit

Roland Dreier wrote:
>  > To repeat what has already been stated, each case was re-evaluated:
>  > http://marc.info/?l=linux-kernel&m=124103527326835&w=2
>  > 
>  > Roland's patch was acked, apparently, _in spite of_ the commonly
>  > accepted readq() definition already being in use!
>  > 
>  > Thusfar, I see two things:
>  > 
>  > (1) years of history has shown that non-atomic readq/writeq on 32-bit
>  > platforms has been sufficient, based on testing and experience.  In
>  > fact, in niu's case, a common readq/writeq would have PREVENTED a bug.
> 
> But the fact that the 32-bit x86 define would have worked for niu is
> pure luck -- if the clear-on-read bits had been in the other half of the
> register in question, then it would have caused a bug.  And I really
> don't trust all ASIC designers writing RTL to think about which half of
> a 64-bit register is going to be read first.

AFAICS things have unerringly occurred in PCI ordering, which is what 
one would expect.

What you call pure luck, others call 100% track record.


> To me, the point is that the current situation of having the defines for
> 32-bit x86 has zero benefit -- not one driver-specific definition can be
> removed, because there are other 32-bit architectures to worry about.

Um, this is precisely what Mitake-san is trying to address, hence the 
discussion...


> And the risk introduced is not zero -- very few devices have 64-bit
> registers and very few drivers use readq or writeq, but perhaps as
> end-to-end 64-bit buses become more prevalent with PCIe, we may see
> more.  And it's certainly the case that emulation 64-bit register
> operations by doing to 32-bit operations on the register halves carries
> a non-zero risk of making the hardware do something wacky.

Again, fear vs. reality, 0% case versus 100% case.

You continue to lack CONCRETE examples of problems, while existing cases 
CONTINUE to work with the obvious ordering.

	Jeff



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