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Message-ID: <20090609142506.GD32703@elte.hu>
Date:	Tue, 9 Jun 2009 16:25:06 +0200
From:	Ingo Molnar <mingo@...e.hu>
To:	Yong Wang <yong.y.wang@...ux.intel.com>
Cc:	Peter Zijlstra <a.p.zijlstra@...llo.nl>,
	Thomas Gleixner <tglx@...utronix.de>,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH -tip] perf_counter/x86: Fix incorrect default branch


* Yong Wang <yong.y.wang@...ux.intel.com> wrote:

> On Tue, Jun 09, 2009 at 03:23:13PM +0200, Ingo Molnar wrote:
> > 
> > * Yong Wang <yong.y.wang@...ux.intel.com> wrote:
> > 
> > > The event selector and UMASK values of Nehalem do not apply to all 
> > > Intel processors.
> > 
> > The idea was to offer _some_ sort of table on new CPUs, instead of 
> > nothing...
> > 
> > Eventually Intel stops changing those model specific index values in 
> > future CPUs and puts them into architectural perfmon, for 
> > fundamental stats like L1/LLC cache statistics.
> > 
> > In that case defaulting to the latest (known) enumeration might work 
> > out to be just the thing used by all future CPUs.
> > 
> > So this is a subtle hint ;-)
> > 
> 
> I see what you mean. You talked about future cpus. But what about 
> those old ones that are not atom, core2 or nehalem? Forget about 
> them?

They dont have X86_FEATURE_ARCH_PERFMON set, right?

I made the switch statement under the assumption that it covers all 
existing arch-perfmon CPU models. If not, the 'default:' placement 
would indeed be buggy.

	Ingo
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