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Message-ID: <4AA08B09.50503@zytor.com> Date: Thu, 03 Sep 2009 20:35:37 -0700 From: "H. Peter Anvin" <hpa@...or.com> To: Tejun Heo <tj@...nel.org> CC: Jeremy Fitzhardinge <jeremy@...p.org>, mingo@...hat.com, linux-kernel@...r.kernel.org, jeremy.fitzhardinge@...rix.com, stable@...nel.org, tglx@...utronix.de, mingo@...e.hu, linux-tip-commits@...r.kernel.org Subject: Re: [tip:x86/asm] x86/i386: Make sure stack-protector segment base is cache aligned On 09/03/2009 07:59 PM, Tejun Heo wrote: > > Another question. Other than saving and loading an extra segment > register on kernel entry/exit, whether using the same or different > segment registers doesn't look like would make difference > performance-wise. If I'm interpreting the wording in the optimization > manual correctly, it means that each non-zero segment based memory > access will be costly regardless of which specific segment register is > in use and there's no way we can merge segment based dereferences for > stackprotector and percpu variables. > It's correct that it doesn't make any difference for access, only for load. -hpa -- H. Peter Anvin, Intel Open Source Technology Center I work for Intel. I don't speak on their behalf. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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