linux-kernel - Re: [tip:x86/asm] x86/i386: Make sure stack-protector segment base is cache aligned

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Message-ID: <4AA08DD3.5010509@kernel.org>
Date:	Fri, 04 Sep 2009 12:47:31 +0900
From:	Tejun Heo <tj@...nel.org>
To:	"H. Peter Anvin" <hpa@...or.com>
CC:	Jeremy Fitzhardinge <jeremy@...p.org>, mingo@...hat.com,
	linux-kernel@...r.kernel.org, jeremy.fitzhardinge@...rix.com,
	stable@...nel.org, tglx@...utronix.de, mingo@...e.hu,
	linux-tip-commits@...r.kernel.org
Subject: Re: [tip:x86/asm] x86/i386: Make sure stack-protector segment base
 is cache aligned

H. Peter Anvin wrote:
> On 09/03/2009 07:59 PM, Tejun Heo wrote:
>> Another question.  Other than saving and loading an extra segment
>> register on kernel entry/exit, whether using the same or different
>> segment registers doesn't look like would make difference
>> performance-wise.  If I'm interpreting the wording in the optimization
>> manual correctly, it means that each non-zero segment based memory
>> access will be costly regardless of which specific segment register is
>> in use and there's no way we can merge segment based dereferences for
>> stackprotector and percpu variables.
>>
> 
> It's correct that it doesn't make any difference for access, only for load.

Heh... here's a naive and hopeful plan.  How about we beg gcc
developers to allow different segment register and offset in newer gcc
versions and then use the same one when building with the new gcc?
This should solve the i386 problem too.  It would be the best as we
get to keep the separate segment register from the userland.  Too
hopeful?

Thanks.

-- 
tejun
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